Exemplary embodiments of the present invention relate to a semiconductor device and a method for fabricating the same, and more particularly, to a 3D non-volatile memory device and a method for fabricating the same.
A non-volatile memory device is a memory device which is capable of maintaining data stored therein, even though power supply is cut off. As a 2D memory device in which memory cells are formed as a single layer on a silicon substrate is reaching its limits in achieving high integration, a 3D non-volatile memory device is being developed, in which memory cells are vertically stacked on a silicon substrate.
Hereafter, the structure of a conventional 3D non-volatile memory device and the concern therein are described with reference to FIG. 1.
FIG. 1 is a cross-sectional view illustrating the structure of the conventional 3D non-volatile memory device and a method for fabricating the same.
Referring to FIG. 1, a source area S is formed by implanting ion impurities into a substrate 10. In general, the source area S may be formed by implanting N-type ion impurities.
A plurality of interlayer dielectric layers 11 and conductive layers 12 are formed on the substrate 10 having the source area S formed therein, and then etched to form a trench exposing the surface of the substrate 10.
A gate dielectric layer 13 is formed on the inner wall of the trench, and a channel layer is buried to form a channel CH. In general, the channel CH may be formed of a poly silicon layer doped with N-type impurities or an undoped poly silicon layer. Through this process, a lower select transistor LST is formed.
On the resultant structure having the lower select transistor LST formed therein, a plurality of interlayer dielectric layers 14 and conductive layers 15 are formed. The number of interlayer dielectric layers 14 and conductive layers 15 to be stacked is determined depending on the number of memory cells to be stacked.
The plurality of interlayer dielectric layers 14 and conductive layers 15 are etched to form a trench exposing the channel CH of the lower select transistor LST.
A charge blocking layer, a charge trap layer, and a tunnel insulating layer are sequentially formed on the inner wall of the trench, and a channel layer is buried to form a channel CH. For convenience of description, the charge blocking layer, the charge trap layer, and the tunnel insulating layer are illustrated as one layer represented by reference numeral 16. In general, the channel CH may be formed of a poly silicon layer doped with N-type impurities or an undoped poly silicon layer. Through this process, a plurality of memory cells MC are formed.
On the resultant structure having the plurality of memory cells MC formed therein, a plurality of interlayer dielectric layers 17 and conductive layers 18 are formed, and then etched to form a trench exposing the channel CH of the memory cells MC.
A gate dielectric layer 19 is formed on the inner wall of the trench, and a channel layer is buried to form a channel CH. In general, the channel CH may be formed of a poly silicon layer doped with N-type impurities or an undoped poly silicon layer. Through this process, an upper select transistor UST is formed.
The plurality of memory cells MC are connected in series between the lower select transistor LST and the upper select transistor UST so as to form one string ST.
In accordance with the conventional 3D non-volatile memory device described above, the process of fabricating the memory device is relatively complex, and the performance of the memory device may be degraded. These concerns are described in more detail as follows.
First, independent processes are performed on a cell area and a peripheral circuit area, respectively. That is, the process of forming the lower select transistor LST, the plurality of memory cells MC, and the upper select transistor UST in the cell area and the process of forming transistors in the peripheral circuit area are separately performed. Therefore, the fabricating process thereof is complex, and the manufacturing cost is relatively high.
Second, since the channels of the select transistors LST and UST are formed of amorphous silicon or polycrystalline silicon, on/off characteristics of the select transistors LST and UST may be degraded, and it may be difficult to control the threshold voltage of the transistors.
Third, since the source area S is formed by implanting N-type ion impurities into the substrate 10, the source area S has high resistance. Therefore, it is highly likely that an error occurs due to the resistance component of the source area S during a read operation.
Fourth, the speed of transferring an erase voltage may be relatively low.
An erase operation is performed by injecting holes into a charge capture layer of a memory cell. Therefore, it is desired to be provided with a P-type source for supplying the holes. In accordance with the conventional 3D non-volatile memory device, however, the channels CH are connected to the N-type source area S, not the P-type source. Therefore, when a positive erase voltage is applied to a bit line and the source area S to perform the erase operation, depletion phenomenon may occur. Accordingly, it takes a considerable amount of time for the positive erase voltage to be transferred to the channels CH of the memory cells, and the speed of the erase operation of the memory device is reduced.
To address such concerns, a method has been developed, which causes gate induced drain leakage (GIDL) current to provide holes. That is, the GIDL current is caused by ramping the bit line, the source area S, the upper select transistor UST, and the lower select transistor LST with certain time differences. As such, the hole of the electron-hole pair which is formed by the intentionally caused GIDL current is supplied to the channel CH of the memory cell MC to perform the erase operation.
However, when the high-level erase voltage is applied to ramp the bit line, the upper select transistor UST, and the lower select transistor LST, the threshold voltages of the upper and lower select transistors UST and LST are varied, and the channels CH are damaged. Then, the reliability of the semiconductor chip may be reduced. Furthermore, although the GIDL current is forcibly caused to supply the holes, it is difficult to uniformly distribute the generated holes to the channels CH of the plurality of memory cells MC. Furthermore, since the bit line, the source area S, the upper select transistor UST, and the lower select transistor LST are all ramped, the power consumption of the semiconductor chip may increase.